| Parameter | Description |
|---|---|
| a0 | 64-bit vector a0 |
| a1 | 64-bit vector a1 |
v64 64-bit vector
Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UHSUB Vd.4H,Vn.4H,Vm.4H