| Parameter | Description |
|---|---|
| a0 | 128-bit vector a0 |
| a1 | 128-bit vector a1 |
| a2 | Int32 a2 |
v128 128-bit vector
Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: USRA Vd.16B,Vn.16B,#n