Method vqdmulh_s16

vqdmulh_s16(v64, v64)

Signed saturating Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are truncated. For rounded results, see SQRDMULH.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULH Vd.4H,Vn.4H,Vm.4H

Declaration

public static v64 vqdmulh_s16(v64 a0, v64 a1)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1

Returns

Type	Description
v64	64-bit vector