Method vpaddlq_s8

vpaddlq_s8(v128)

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SADDLP Vd.8H,Vn.16B

Declaration

public static v128 vpaddlq_s8(v128 a0)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0

Returns

Type	Description
v128	128-bit vector