Method vmulx_laneq_f64

vmulx_laneq_f64(v64, v128, Int32)

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If one value is zero and the other value is infinite, the result is 2.0. In this case, the result is negative if only one of the values is negative, otherwise the result is positive.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMULX Dd,Dn,Vm.D[lane]

Declaration

public static v64 vmulx_laneq_f64(v64 a0, v128 a1, int a2)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v128	a1	128-bit vector a1
Int32	a2	Lane index to a1. Must be an immediate in the range of [0..1]

Returns

Type	Description
v64	64-bit vector