Method vhsub_s8

vhsub_s8(v64, v64)

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHSUB Vd.8B,Vn.8B,Vm.8B

Declaration

public static v64 vhsub_s8(v64 a0, v64 a1)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1

Returns

Type	Description
v64	64-bit vector