Method vzip1_s16

vzip1_s16(v64, v64)

Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.This instruction can be used with ZIP2 to interleave two vectors.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: ZIP1 Vd.4H,Vn.4H,Vm.4H

Declaration

public static v64 vzip1_s16(v64 a0, v64 a1)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1

Returns

Type	Description
v64	64-bit vector