Method vrsqrts_f32
vrsqrts_f32(v64, v64)
Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FRSQRTS Vd.2S,Vn.2S,Vm.2S
Declaration
public static v64 vrsqrts_f32(v64 a0, v64 a1)
Parameters
Type |
Name |
Description |
v64 |
a0 |
64-bit vector a0
|
v64 |
a1 |
64-bit vector a1
|
Returns
Type |
Description |
v64 |
64-bit vector
|
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