Method vqrshld_u64

vqrshld_u64(ulong, long)

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift. The results are rounded. For truncated results, see UQSHL.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: UQRSHL Dd,Dn,Dm

Declaration

public static ulong vqrshld_u64(ulong a0, long a1)

Parameters

Type	Name	Description
ulong	a0	UInt64 a0
long	a1	Int64 a1

Returns

Type	Description
ulong	UInt64