Method vqrdmlsh_lane_s16

vqrdmlsh_lane_s16(v64, v64, v64, int)

Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and subtracts the most significant half of the final results from the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLSH Vd.4H,Vn.4H,Vm.H[lane]

Declaration

public static v64 vqrdmlsh_lane_s16(v64 a0, v64 a1, v64 a2, int a3)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1
v64	a2	64-bit vector a2
int	a3	Lane index to a2. Must be an immediate in the range of [0..3]

Returns

Type	Description
v64	64-bit vector