Method vqrdmlahs_lane_s32
vqrdmlahs_lane_s32(Int32, Int32, v64, Int32)
Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element). This instruction multiplies the vector elements of the first source SIMD&FP register with the value of a vector element of the second source SIMD&FP register without saturating the multiply results, doubles the results, and accumulates the most significant half of the final results with the vector elements of the destination SIMD&FP register. The results are rounded.If any of the results overflow, they are saturated. The cumulative saturation bit, FPSR.QC, is set if saturation occurs.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMLAH Sd,Sn,Vm.S[lane]
Declaration
public static Int32 vqrdmlahs_lane_s32(Int32 a0, Int32 a1, v64 a2, Int32 a3)
Parameters
Type |
Name |
Description |
Int32 |
a0 |
Int32 a0
|
Int32 |
a1 |
Int32 a1
|
v64 |
a2 |
128-bit vector a2
|
Int32 |
a3 |
Lane index to a2. Must be an immediate in the range of [0..1]
|
Returns
Type |
Description |
Int32 |
Int32
|
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