Method vqdmull_laneq_s16

vqdmull_laneq_s16(v64, v128, Int32)

Signed saturating Doubling Multiply Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMULL instruction extracts the first source vector from the lower half of the first source register, while the SQDMULL2 instruction extracts the first source vector from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMULL Vd.4S,Vn.4H,Vm.H[lane]

Declaration

public static v128 vqdmull_laneq_s16(v64 a0, v128 a1, Int32 a2)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v128	a1	128-bit vector a1
Int32	a2	Lane index to a1. Must be an immediate in the range of [0..7]

Returns

Type	Description
v128	128-bit vector