Method vqdmlsl_lane_s16

vqdmlsl_lane_s16(v128, v64, v64, int)

Signed saturating Doubling Multiply-Subtract Long (by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.The SQDMLSL instruction extracts vector elements from the lower half of the first source register, while the SQDMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]

Declaration

public static v128 vqdmlsl_lane_s16(v128 a0, v64 a1, v64 a2, int a3)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
v64	a1	64-bit vector a1
v64	a2	64-bit vector a2
int	a3	Lane index to a2. Must be an immediate in the range of [0..3]

Returns

Type	Description
v128	128-bit vector