Method vpaddd_f64

vpaddd_f64(v128)

Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FADDP Dd,Vn.2D

Declaration

public static double vpaddd_f64(v128 a0)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0

Returns

Type	Description
double	Double