Method vmull_n_s16

vmull_n_s16(v64, short)

Signed Multiply Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMULL instruction extracts vector elements from the lower half of the first source register, while the SMULL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMULL Vd.4S,Vn.4H,Vm.H[0]

Declaration

public static v128 vmull_n_s16(v64 a0, short a1)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
short	a1	Int16 a1

Returns

Type	Description
v128	128-bit vector