Method vmlsl_s16

vmlsl_s16(v128, v64, v64)

Signed Multiply-Subtract Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.The SMLSL instruction extracts vector elements from the lower half of the first source register, while the SMLSL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLSL Vd.4S,Vn.4H,Vm.4H

Declaration

public static v128 vmlsl_s16(v128 a0, v64 a1, v64 a2)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
v64	a1	64-bit vector a1
v64	a2	64-bit vector a2

Returns

Type	Description
v128	128-bit vector