Method vmlal_laneq_s16

vmlal_laneq_s16(v128, v64, v128, int)

Signed Multiply-Add Long (vector, by element). This instruction multiplies each vector element in the lower or upper half of the first source SIMD&FP register by the specified vector element in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are signed integer values.The SMLAL instruction extracts vector elements from the lower half of the first source register, while the SMLAL2 instruction extracts vector elements from the upper half of the first source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SMLAL Vd.4S,Vn.4H,Vm.H[lane]

Declaration

public static v128 vmlal_laneq_s16(v128 a0, v64 a1, v128 a2, int a3)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
v64	a1	64-bit vector a1
v128	a2	128-bit vector a2
int	a3	Lane index to a2. Must be an immediate in the range of [0..7]

Returns

Type	Description
v128	128-bit vector