Method vfmsd_laneq_f64

vfmsd_laneq_f64(Double, Double, v128, Int32)

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Dd,Dn,Vm.D[lane]

Declaration

public static Double vfmsd_laneq_f64(Double a0, Double a1, v128 a2, Int32 a3)

Parameters

Type	Name	Description
Double	a0	Double a0
Double	a1	Double a1
v128	a2	128-bit vector a2
Int32	a3	Lane index to a2. Must be an immediate in the range of [0..1]

Returns

Type	Description
Double	Double