Method vfms_f64

vfms_f64(v64, v64, v64)

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMSUB Dd,Dn,Dm,Da

Declaration

public static v64 vfms_f64(v64 a0, v64 a1, v64 a2)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1
v64	a2	64-bit vector a2

Returns

Type	Description
v64	64-bit vector