Method vcltz_s8
vcltz_s8(v64)
Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLT Vd.8B,Vn.8B,#0
Declaration
public static v64 vcltz_s8(v64 a0)
Parameters
Type | Name | Description |
---|---|---|
v64 | a0 | 64-bit vector a0 |
Returns
Type | Description |
---|---|
v64 | 64-bit vector |