Method vcltd_s64

vcltd_s64(long, long)

Compare signed Less than (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first signed integer value is less than the second signed integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMGT Dd,Dm,Dn

Declaration

public static ulong vcltd_s64(long a0, long a1)

Parameters

Type	Name	Description
long	a0	Int64 a0
long	a1	Int64 a1

Returns

Type	Description
ulong	UInt64