Method vclezq_s64

vclezq_s64(v128)

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: CMLE Vd.2D,Vn.2D,#0

Declaration

public static v128 vclezq_s64(v128 a0)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0

Returns

Type	Description
v128	128-bit vector