Method vsubw_s16

vsubw_s16(v128, v64)

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.The SSUBW instruction extracts the second source vector from the lower half of the second source register, while the SSUBW2 instruction extracts the second source vector from the upper half of the second source register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSUBW Vd.4S,Vn.4S,Vm.4H

Declaration

public static v128 vsubw_s16(v128 a0, v64 a1)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
v64	a1	64-bit vector a1

Returns

Type	Description
v128	128-bit vector