Method vsrad_n_s64
vsrad_n_s64(Int64, Int64, Int32)
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SSRA Dd,Dn,#n
Declaration
public static Int64 vsrad_n_s64(Int64 a0, Int64 a1, Int32 a2)Parameters
| Type | Name | Description |
|---|---|---|
| Int64 | a0 | Int64 a0 |
| Int64 | a1 | Int64 a1 |
| Int32 | a2 | Int32 a2 |
Returns
| Type | Description |
|---|---|
| Int64 | Int64 |