Method vshrn_n_s64

vshrn_n_s64(v128, Int32)

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN Vd.2S,Vn.2D,#n

Declaration

public static v64 vshrn_n_s64(v128 a0, Int32 a1)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
Int32	a1	Int32 a1

Returns

Type	Description
v64	64-bit vector