Method vshrn_high_n_s64

vshrn_high_n_s64(v64, v128, Int32)

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.The RSHRN instruction writes the vector to the lower half of the destination register and clears the upper half, while the RSHRN2 instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SHRN2 Vd.4S,Vn.2D,#n

Declaration

public static v128 vshrn_high_n_s64(v64 a0, v128 a1, Int32 a2)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v128	a1	128-bit vector a1
Int32	a2	Int32 a2

Returns

Type	Description
v128	128-bit vector