Method vrshld_s64

vrshld_s64(Int64, Int64)

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see SSHL.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SRSHL Dd,Dn,Dm

Declaration

public static Int64 vrshld_s64(Int64 a0, Int64 a1)

Parameters

Type	Name	Description
Int64	a0	Int64 a0
Int64	a1	Int64 a1

Returns

Type	Description
Int64	Int64