Method vrev64q_s8
vrev64q_s8(v128)
Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: REV64 Vd.16B,Vn.16B
Declaration
public static v128 vrev64q_s8(v128 a0)Parameters
| Type | Name | Description |
|---|---|---|
| v128 | a0 | 128-bit vector a0 |
Returns
| Type | Description |
|---|---|
| v128 | 128-bit vector |