Method vqrdmulh_lane_s16

vqrdmulh_lane_s16(v64, v64, Int32)

Signed saturating Rounding Doubling Multiply returning High half (by element). This instruction multiplies each vector element in the first source SIMD&FP register by the specified vector element of the second source SIMD&FP register, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.The results are rounded. For truncated results, see SQDMULH.If any of the results overflows, they are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]

Declaration

public static v64 vqrdmulh_lane_s16(v64 a0, v64 a1, Int32 a2)

Parameters

Type	Name	Description
v64	a0	64-bit vector a0
v64	a1	64-bit vector a1
Int32	a2	Lane index to a1. Must be an immediate in the range of [0..3]

Returns

Type	Description
v64	64-bit vector