Method vfmsq_n_f64

vfmsq_n_f64(v128, v128, Double)

Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register. All the values in this instruction are floating-point values.This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Equivalent instruction: FMLS Vd.2D,Vn.2D,Vm.D[0]

Declaration

public static v128 vfmsq_n_f64(v128 a0, v128 a1, Double a2)

Parameters

Type	Name	Description
v128	a0	128-bit vector a0
v128	a1	128-bit vector a1
Double	a2	Double a2

Returns

Type	Description
v128	128-bit vector